test_num | device_name | reg_name | offset | alter_value | expect_value |
testcase1_(core_0_uart_0) | core_0_uart_0 | RBR | 0x0 | 0xFFFFF | 0x0 |
testcase2_(core_0_uart_0) | core_0_uart_0 | THR | 0x0 | 0xFFFFF | 0x0 |
testcase3_(core_0_uart_0) | core_0_uart_0 | IER | 0x2 | 0xFFFFF | 0xffff |
testcase4_(core_0_uart_0) | core_0_uart_0 | FCR | 0x4 | 0xFFFFF | 0x1 |
testcase5_(core_0_uart_0) | core_0_uart_0 | IIR | 0x4 | 0xFFFFF | 0x1 |
testcase6_(core_0_uart_0) | core_0_uart_0 | LCR | 0x6 | 0xFFFFF | 0xffff |
testcase7_(core_0_uart_0) | core_0_uart_0 | MCR | 0x8 | 0xFFFFF | 0xffff |
testcase8_(core_0_uart_0) | core_0_uart_0 | LSR | 0xa | 0xFFFFF | 0xffff |
testcase9_(core_0_uart_0) | core_0_uart_0 | SCR | 0xe | 0xFFFFF | 0xffff |
testcase10_(core_0_uart_0) | core_0_uart_0 | DLL | 0x10 | 0xFFFFF | 0xffff |
testcase11_(core_0_uart_0) | core_0_uart_0 | DLH | 0x12 | 0xFFFFF | 0xffff |
testcase12_(core_0_uart_0) | core_0_uart_0 | PWREMU_MGMT | 0x18 | 0xFFFFF | 0xffff |
testcase1_(core_0_timer_0) | core_0_timer_0 | tim | 0x0 | 0xFFFFF | 0xffff |
testcase2_(core_0_timer_0) | core_0_timer_0 | prd | 0x4 | 0xFFFFF | 0x0 |
testcase3_(core_0_timer_0) | core_0_timer_0 | tcr | 0x8 | 0xFFFFF | 0x0 |