tst_num,device_name,reg_name,offset,init_value,alter_value,expect_value,actual_value,test_result
testcase1_(core_0_uart_0),core_0_uart_0,RBR,0x0,0x0,0xfffff,0x0,0x0,true
testcase2_(core_0_uart_0),core_0_uart_0,THR,0x0,0x0,0xfffff,0x0,0x0,true
testcase3_(core_0_uart_0),core_0_uart_0,IER,0x2,0x0,0xfffff,0xffff,0xffff,true
testcase4_(core_0_uart_0),core_0_uart_0,FCR,0x4,0x1,0xfffff,0x1,0x1,true
testcase5_(core_0_uart_0),core_0_uart_0,IIR,0x4,0x1,0xfffff,0x1,0x1,true
testcase6_(core_0_uart_0),core_0_uart_0,LCR,0x6,0x0,0xfffff,0xffff,0xffff,true
testcase7_(core_0_uart_0),core_0_uart_0,MCR,0x8,0x0,0xfffff,0xffff,0xffff,true
testcase8_(core_0_uart_0),core_0_uart_0,LSR,0xa,0x20,0xfffff,0xffff,0xffff,true
testcase9_(core_0_uart_0),core_0_uart_0,SCR,0xe,0x0,0xfffff,0xffff,0xffff,true
testcase10_(core_0_uart_0),core_0_uart_0,DLL,0x10,0x0,0xfffff,0xffff,0xffff,true
testcase11_(core_0_uart_0),core_0_uart_0,DLH,0x12,0x0,0xfffff,0xffff,0xffff,true
testcase12_(core_0_uart_0),core_0_uart_0,PWREMU_MGMT,0x18,0x0,0xfffff,0xffff,0xffff,true
testcase1_(core_0_timer_0),core_0_timer_0,tim,0x0,0x345,0xfffff,0xffff,0xffff,true
testcase2_(core_0_timer_0),core_0_timer_0,prd,0x4,0x0,0xfffff,0x0,0x0,true
testcase3_(core_0_timer_0),core_0_timer_0,tcr,0x8,0x0,0xfffff,0x0,0x0,true